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MT9041
Multiple Output Trunk PLL Advance Information
Features
* Provides T1 and E1 clocks, and ST-BUS/GCI framing signals locked to an input reference of either 8 kHz (frame pulse), 1.544 MHz (T1), or 2.048 MHz (E1) Meets AT & T TR62411 and ETSI ETS 300 011 specifications for a 1.544 MHz (T1), or 2.048 MHz (E1) input reference Typical unfiltered intrinsic output jitter is 0.013 UI peak-to-peak Jitter attenuation of 15 dB @ 10 Hz, 34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz Low power CMOS technology
ISSUE 1
May 1995
Ordering Information MT9041AP 28 Pin PLCC -40 C to +85 C
*
Description
The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.544 MHz, or 8 kHz reference. The T1 and E1 outputs are fully compliant with AT & T TR62411 (ACCUNET(R) T1.5) and ETSI ETS 300 011 intrinsic jitter and jitter transfer specifications, respectively, when synchronized to primary reference input clock rates of either 1.544 MHz or 2.048 MHz. The PLL also provides additional high speed output clocks at rates of 3.088 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz for backplane synchronization.
* * *
Applications
* * * Synchronization and timing control for T1 and E1 digital transmission links ST-BUS clock and frame pulse sources Primary Trunk Rate Converters
VDD
VSS
MCLKo
MCLKi
C3 PRI
Phase Detector
Loop Filter
C1.5 DCO Interface Circuit C16 C8 C4 C2 F0o FP8-STB FP8-GCI
IC0
IC1
Mode Select
Divider
MS
FSEL1
FSEL2
Figure 1 - Functional Block Diagram
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MT9041
IC0 VSS RST FSEL1 FSEL2
Advance Information
VDD MCLKo MCLKi FP8-GCI F0o FP8-STB C1.5
4 3 2 1 28 27 26 5 25 24 6 7 23 22 8 21 9 10 20 19 11 12 13 14 15 16 17 18
PRI IC0
IC0 IC0 MS IC0 IC0 IC1 IC0
Figure 2 - Pin Connections
Pin Description
Pin # 1 2,3 4 Name VSS IC0 PRI Description Negative Power Supply Voltage. Nominally 0 Volts. Internal Connection 0. Connect to VSS. Primary Reference Input (TTL compatible). This input (either 8 kHz, 1.544 MHz, or 2.048 MHz as controlled by the input frequency selection pins) is used as the primary reference source for PLL synchronization. Positive Supply Voltage. Nominally +5 volts. Master Clock Oscillator Output. This is a CMOS buffered output used for driving a 20 MHz crystal. Master Clock Oscillator Input. This is a CMOS input for a 20 MHz crystal or crystal oscillator. Signals should be DC coupled to this pin.
5 6 7 8
VDD MCLKo MCLKi
FP8-GCI Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that indicates the start of the active GCI-BUS frame. The pulse width is based upon the period of the 8.192 MHz synchronization clock. F0o Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that indicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 4.096 MHz synchronization clock. This is an active low signal.
9
10
FP8-STB Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that indicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 8.192 MHz synchronization clock. C1.5 C3 C2 C4 VSS C8 Clock 1.544 MHz (CMOS compatible). This ouput is a 1.544 MHz (T1) output clock locked to the reference input signal. Clock 3.088 MHz (CMOS compatible). This output is a 3.088 MHz output clock locked to the reference input signal. Clock 2.048 MHz (CMOS compatible). This output is a 2.048 MHz (E1) output clock locked to the reference input signal. Clock 4.096 MHz (CMOS compatible). This output is a 4.096 MHz output clock locked to the reference input signal. Negative Power Supply Voltage. Nominally 0 Volts. Clock 8.192 MHz (CMOS compatible). This output is an 8.192 MHz output clock locked to the reference input signal.
11 12 13 14 15 16
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C3 C2 C4 VSS C8 C16 VDD
Advance Information
Pin Description (continued)
Pin # 17 18 19 20 21, 22 23 24, 25 26 Name C16 VDD IC0 IC1 IC0 MS IC0 FSEL2 Description
MT9041
Clock 16.384 MHz (CMOS compatible). This output is a 16.384 MHz output clock locked to the reference input signal. Positive Supply Voltage. Nominally +5 volts. Internal Connection 0. Connect to VSS. Internal Connection 1. Leave open circuit. Internal Connection 0. Connect to VSS. Mode Select Input (TTL compatible). This input selects the PLL mode of operation (i.e. , NORMAL or FREERUN, see Table 1). Internal Connection 0. Connect to VSS. Frequency Select - 2 Input (TTL compatible). This input, in conjunction with FSEL1, selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz; see Table 3). Frequency Select - 1 Input (TTL compatible). This input, in conjunction with FSEL2, selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz; see Table 3). Reset (TTL compatible). This input (active LOW) puts the MT9041 in its reset state. To guarantee proper operation, the device must be reset after power-up. The time constant for a power-up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RST pin must be held low for a minimum of 60 nsec to reset the device.
27
FSEL1
28
RST
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MT9041
Functional Description
The MT9041 is a fully digital, phase-locked loop designed to provide timing references to interface circuits for T1 and E1 Primary Rate Digital Transmission links. As shown in Figure 1, the PLL employs a high resolution Digitally Controlled Oscillator (DCO) to generate the T1 and E1 outputs. The interface circuit on the output of the DCO generates 1.544 MHz (C1.5), 3.088 MHz (C3), 2.048 MHz (C2), 4.096 MHz (C4), 8.192 MHz (C8), 16.384 MHz (C16), and three 8 kHz frame pulses F0o, FP8STB, and FP8-GCI.
Advance Information
is controlled by the logic levels of FSEL1 and FSEL2, as shown in Table 2. This variety of input frequencies was chosen to allow the generation of all the necessary T1 and E1 clocks from either a T1, E1 or frame pulse reference source. FSEL 2 0 0 1 1 FSEL 1 0 1 0 1 Input Reference Frequency Reserved 8 kHz 1.544 MHz 2.048 MHz
Table 2 - Input Frequency Selection of the MT9041
fref
Phase Detector
Loop Filter
PLL Measures of Performance
DCO
fsync
To meet the requirements of AT & T TR62411 and ETSI 300 011, the following PLL performance parameters were measured: * locking range and lock time free-run accuracy intrinsic jitter jitter transfer function output jitter spectrum wander
Divider
Figure 3 - PLL Block Diagram As shown in Figure 3, the PLL of the MT9041 consists of a phase detector (PD), a loop filter, a high resolution DCO, and a digital frequency divider. The digitally controlled oscillator (DCO) is locked in frequency (n x fref) to one of three possible reference frequencies, configured using pins FSEL1 and FSEL2. The PLL is capable of providing a full range of E1/T1 clock signals synchronized to the primary PRI input. The loop filter is a first order lowpass structure that provides approximately a 2 Hz bandwidth.
* * * * *
Locking Range and Lock Time The locking range of the PLL is the range that the input reference frequency can be deviated from its nominal frequency while the output signals maintain synchronization. The relevant value is usually specified in parts-per-million (ppm). For both the T1 and E1 outputs, lock was maintained while an 8 kHz input was varied between 7900 Hz to 8100 Hz (corresponding to 12500 ppm). This is well beyond the required 100 ppm. The lock range of 12500 ppm also applies to 1.544 MHz and 2.048 MHz reference inputs. The lock time is a measure of how long it takes the PLL to reach steady state frequency after a frequency step on the reference input signal. The locking time is measured by applying an 8000 Hz signal to the primary reference and an 8000.8 Hz (+100 ppm) to the secondary reference. The output is monitored with a time interval analyzer during slow periodic rearrangements on the reference inputs. The lock time for both the T1 and E1 outputs is approximately 311 ms, which is well below the required lock time of 1.0 seconds.
Modes of Operation
The MT9041 can operate in one of two modes, NORMAL or FREERUN, as controlled by mode select pin MS (see Table 1).
MS 0 1
Description of Operation NORMAL FREERUN
Table 1- Operating Modes of the MT9041 Normal Mode . There are three possible input frequencies for selection as the primary reference clock. These are 8 kHz, 1.544 MHz or 2.048 MHz. Frequency selection
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Advance Information
Freerun Accuracy The Freerun accuracy of the PLL is a measure of how accurately the PLL can reproduce the desired output frequency. The freerun accuracy is a function of master clock frequency which must be 20 MHz 32 ppm in order to meet AT & T TR62411 and ETSI specifications. Jitter Performance The output jitter of a digital trunk PLL is composed of intrinsic jitter, measured using a jitter free reference clock, and frequency dependent jitter, measured by applying known levels of jitter on the references clock. The jitter spectrum indicates the frequency content of the output jitter. Intrinsic Jitter Intrinsic jitter is the jitter added to an output signal by the processing device, in this case the enhanced PLL. Tables 3 and 4 show the average measured intrinsic jitter of the T1 and E1 outputs. Each measurement is an average based upon a 100 ppm deviation (in steps of 20 ppm) on the input reference clock. Jitter on the master clock will increase intrinsic jitter of the device, hence attention to minimization of master clock jitter is required. Jitter Transfer Function
MT9041
The jitter transfer function is a measure of the transfer characteristics of the PLL to frequency specific jitter on the referenced input of the PLL. It is directly linked to the loop bandwidth and the magnitude of the phase error suppression characteristics of the PLL. It is measured by applying jitter of specific magnitude and frequencies to the input of the PLL, then measuring the magnitude of the output jitter (both filtered and unfiltered) on the T1 or E1 output. Care must be taken when measuring the transfer characteristics to ensure that critical jitter alias frequencies are included in the measurement (i.e., for digital phase locked loops using an 8 kHz input). Tables 5 and 6 provide measured results for the jitter transfer characteristics of the PLL for both a 1.544 MHz and 2.048 MHz reference input clock. The transfer characteristics for an 8 kHz reference input will be the same. Figures 4 and 5 show the jitter attenuation performance of the T1 and E1 outputs plotted against AT & T TR62411 and ETSI requirements, respectively.
Output Jitter in UIp-p Reference Input 8 kHz 1.544 MHz 2.048 MHz FLT0 Unfiltered .011 .011 .011 FLT1 10Hz - 8kHz .004 .001 .001 FLT2 10Hz - 40kHz .006 .002 .002 FLT3 8kHz - 40kHz .002 .001 .001
Table 3 -Typical Intrinsic Jitter for the T1 Output
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
Output Jitter in UIp-p Reference Input 8 kHz 1.544 MHz 2.048 MHz FLT0 Unfiltered .011 .011 .011 FLT1 20Hz - 100kHz .002 .002 .002 FLT2 700Hz - 100kHz .002 .002 .002
Table 4 - Typical Intrinsic Jitter for the E1 Output
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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MT9041
Advance Information
Measured Jitter Output (UIp-p) Input Jitter Modulation Frequency (Hz) Input Jitter Magnitude (UIp-p) T1 Reference Input Output Jitter Magnitude (UIp-p) 2.42 1.62 .900 .375 .060 .032 .015 .003 .003 .003 .003 .003 .003 .003 .003 .003 .003 Jitter Attenuation (dB) 18.34 21.83 26.94 34.54 44.44 47.96 53.38 48.52 50.83 50.83 50.83 50.83 50.83 50.83 50.83 50.83 42.50 E1 Reference Input Output Jitter Magnitude (UIp-p) 2.41 1.618 .908 .376 .060 .032 .015 .003 .003 .003 .003 .003 .003 .003 .003 .003 .003 Jitter Attenuation (dB) 18.38 21.84 26.86 34.52 44.44 47.96 53.38 48.52 50.83 50.83 50.83 50.83 50.83 50.83 50.83 50.83 42.50
10 20 40 100 330 500 1000 5000 7900 7950 7980 7999 8001 8020 8050 8100 10000
20 20 20 20 10 8 7 0.8 1.044 1.044 1.044 1.044 1.044 1.044 1.044 1.044 0.4
Table 5 - Typical Jitter Transfer Function for the T1 Output
Notes 1) For input jitter from 10 kHz to 100 kHz, the jitter attenuation is of such magnitude that intrinsic jitter dominates the output signal, rendering the jitter transfer function unmeasurable. 2) Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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Advance Information
Measured Jitter Output (UIp-p) Input Jitter Modulation Frequency (Hz) Input Jitter Magnitude (UIp-p) T1 Reference Input Output Jitter Magnitude (UIp-p) .355 .186 .095 .039 .021 .012 .006 .002 .002 .002 .002 .002 .002 .002 .002 .004 .004 Jitter Attenuation (dB) 12.52 18.13 23.97 31.70 37.08 41.94 47.96 54.35 54.35 54.35 54.35 54.35 54.35 54.35 54.35 38.84 33.98
MT9041
E1 Reference Input Output Jitter Magnitude (UIp-p) .351 .185 .096 .039 .020 .012 .007 .002 .002 .002 .002 .002 .002 .002 .002 .003 .003 Jitter Attenuation (dB) 12.62 18.18 23.88 31.70 37.50 41.94 46.62 54.35 54.35 54.35 54.35 54.35 54.35 54.35 54.35 41.34 36.48
10 20 40 100 200 400 1000 7900* 7950* 7980* 7999* 8001* 8020* 8050* 8100* 10000 100000
1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.044 1.044 1.044 1.044 1.044 1.044 1.044 1.044 0.35 0.20
Table 6 - Typical Jitter Transfer Function for the E1 Output
Notes 1) For input jitter from 10 kHz to 100 kHz, the jitter attenuation is of such magnitude that intrinsic jitter dominates the output signal, rendering the jitter transfer function unmeasurable. 2) Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * Output jitter dominated by intrinsic jitter.
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MT9041
0 b) 10 a)
Advance Information
SLOPE -20 dB PER DECADE JITTER ATTENUATION (dB) 20
30 SLOPE -40 dB PER DECADE
40
50
60
1
10
20
100 Frequency (Hz)
300
1K
10K
Figure 4 - Typical Jitter Attenuation for T1 Output
dB
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JITTER ATTENUATION (dB)
-0.5 0
19.5
10
40 Frequency (Hz)
400
10K
Figure 5 - Typical Jitter Attenuation for E1 Output
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Advance Information
MT9041
Absolute Maximum Ratings*- Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter 1 2 3 4 5 6 7 Supply Voltage Voltage on any pin Input/Output Diode Current Output Source or Sink Current DC Supply or Ground Current Storage Temperature Package Power Dissipation PLCC Symbol VDD VI IIK/OK IO IDD/ISS TST PD -55 Min -0.3 VSS-0.3 Max 7.0 VDD+0.3 150 150 300 125 900 Units V V mA mA mA C mW
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 Supply Voltage Input HIGH Voltage Input LOW Voltage Operating Temperature Sym VDD VIH VIL TA Min 4.5 2.0 VSS -40 25 Typ 5.0 Max 5.5 VDD 0.8 85 Units V V V C Test Conditions
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics VDD =5.0 V10%; VSS =0V; TA =-40 to 85C.
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6
S U P I N O U T
Sym IDD
Min
Typ 55
Max
Units mA
Test Conditions Under operating condition
Supply Current Input HIGH voltage Input LOW voltage Output current HIGH Output current LOW Leakage current on all inputs
VIH VIL IOH IOL IIL
2.0 0.8 -4 4 10
V V mA mA A VOH=2.4 V VOL=0.4 V VIN=VSS
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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MT9041
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 O U T P U T S I N P U T S 8 kHz reference clock period 1.544 MHz reference clock period 2.048 MHz reference clock period Input to output propagation delay with an 8 kHz reference clock Input to output propagation delay with a 1.544 MHz reference clock Input to output propagation delay with a 2.048 MHz reference clock Input rise time (except MCLKi) Input fall time (except MCLKi) Delay between C1.5 and C2 Frame pulse F0o output pulse width Frame pulse F0o output rise time Frame pulse F0o output fall time Frame pulse FP8-STB output pulse width Frame pulse FP8-STB output rise time Frame pulse FP8-STB output fall time Frame pulse FP8-GCI output pulse width Frame pulse FP8-GCI output rise time Frame pulse FP8-GCI output fall time C1.5 clock period C1.5 clock output rise time C1.5 clock output fall time C1.5 clock output duty cycle C3 clock period C3 clock output rise time C3 clock output fall time C3 clock output duty cycle C2 clock period C2 clock output rise time C2 clock output fall time C2 clock output duty cycle tP-C2 tRC2 tFC2 tP-C3 tRC3 tFC3 tD-20-15 tW-F0o tR-F0o tF-F0o tW-FP8STB tR-FP8STB tF-FP8STB tW-FP8GCI tR-FP8GCI tF-FP8GCI tP-C1.5 tRC1.5 tFC1.5 18 244 5 5 122 5 5 122 5 5 648 5 5 50 324 5 5 50 488 5 5 50 9 9 9 9 9 9 9 9 9 9 9 9 Sym tP8R tP15R tP20R tPD8 tPD15 tPD20 Min Typ 125 648 488 183 243 183 8 8 Max
Advance Information
AC Electrical Characteristics (see Fig. 6)-Voltages are with respect to ground (VSS) unless otherwise stated.
Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns % ns ns ns % ns ns ns % Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF Load = 85pF MCLKi = 20.000 000MHz MCLKi = 20.000 000MHz MCLKi = 20.000 000MHz Test Conditions
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Advance Information
MT9041
Sym tP-C4 tRC4 tFC4 Min Typ 244 5 5 50 tP-C8 tRC8 tFC8 122 5 5 50 tP-C16 tRC16 tFC16 43 61 5 5 50 9 9 55 9 9 9 9 Max Units ns ns ns % ns ns ns % ns ns ns % Load = 85pF Load = 85pF Duty cycle on MCLKi =50% Load = 85pF Load = 85pF Load = 85pF Load = 85pF Test Conditions
AC Electrical Characteristics (see Fig. 6)-Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 31 32 33 34 35 36 37 38 39 40 41 42 O U T P U T S C4 clock period C4 clock output rise time C4 clock output fall time C4 clock output duty cycle C8 clock period C8 clock output rise time C8 clock output fall time C8 clock output duty cycle C16 clock period C16 clock output rise time C16 clock output fall time C16 clock output duty cycle
-Typical
-Timing is over recommended temperature & power supply voltages. figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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tPD-8 PRI- 8 kHz tPD-20 PRI-2.048 MHz tW-F0o F0o tW-FP8STB FP8-STB tW-FP8GCI FP8-GCI tP-C16 C16 tP-C8 C8 tP-C4 C4 tP-C2 C2 tD-20-15 C3 tP-C3
Advance Information
C1.5 tPD-15 PRI-1.544 MHz tP-C1.5
Figure 6 - Timing Information for MT9041
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MT9041
AC Electrical Characteristics (see Fig. 7) - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1C L 2 O 3C K 4 Master clock input rise time Master clock input fall time Master clock frequency Duty Cycle of the master clock Sym trMCLKi tfMCLKi tpMCLKi 19.99936 40 20 50 Min Typ Max 4 4 20.000640 60 Units ns ns MHz % Test Conditions
Timing is over recommended temperature & power supply voltages Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing
trMCLK MCLKi 2.4V 1.5V 0.4V
tfMCLK
Figure 7 - Master Clock Input
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MT9041
Notes:
Advance Information
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